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low power, precision analog microcontroller with dual sigma-delta adcs, arm cortex-m3 data sheet ADUCM362 / aducm363 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features pin compatible with the aducm360 / aducm361 analog input/output dual 24-bit adcs ( ADUCM362 ) single 24-bit adc ( aducm363 ) programmable adc output rate (3.5 hz to 3.906 khz) simultaneous 50 hz/60 hz noise rejection at 50 sps continuous conversion mode at 16.67 sps single conversion mode flexible input mux for input channel selection to both adcs two 24-bit multichannel adcs (adc0 and adc1) 6 differential or 12 single-ended input channels 4 internal channels for monitoring dac, temperature sensor, iovdd/4, and avdd/4 (adc1 only) programmable gain (1 to 128) gain of 1 with input buffer on/off supported rms noise: 52 nv at 3.53 hz, 200 nv at 50 hz programmable sensor excitation current sources on-chip precision voltage reference two external reference options supported by both adcs single 12-bit voltage output dac npn mode for 4 ma to 20 ma loop applications microcontroller arm cortex-m3 32-bit processor serial wire download and debug internal watch crystal for wake-up timer 16 mhz oscillator with 8-way programmable divider memory up to 256 kb flash/ee memory, 24 kb sram in-circuit debug/download via serial wire and uart power supply range: 1.8 v to 3.6 v (maximum) power consumption, mcu active mode core consumes 290 a/mhz overall system current consumption of 1.0 ma with core operating at 500 khz (both adcs on, input buffers off, pga gain of 4, one spi port on, and all timers on) power consumption, power-down mode: 4 a (wake-up timer active) on-chip peripherals 2 uart, i 2 c, and 2 spi serial input/output (i/o) 16-bit pulse-width modulation (pwm) controller 19-pin multifunction gpio port 2 general-purpose timers wake-up timer/watchdog timer multichannel dma and interrupt controller dma support for both spi channels package and temperature range 48-lead, 7 mm 7 mm lfcsp specified for ?40c to +125c operation development tools low cost quickstart development system third-party compiler and emulator tool support multiple diagnostic functions that support sil certification applications industrial automation and process control intelligent precision sensing systems 4 ma to 20 ma loop-powered smart sensor systems medical devices, patient monitoring
ADUCM362/aducm363 data sheet rev. 0| page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? functional block diagrams ............................................................. 4 ? specifications ..................................................................................... 6 ? microcontroller electrical specifications .................................. 6 ? rms noise resolution of adc0 and adc1 .......................... 11 ? i 2 c timing specifications .......................................................... 15 ? spi timing specifications ......................................................... 16 ? absolute maximum ratings ......................................................... 18 ? thermal resistance .................................................................... 18 ? esd caution................................................................................ 18 ? pin configuration and function descriptions ........................... 19 ? typical performance characteristics ........................................... 22 ? typical system configuration ...................................................... 23 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 24 ? revision history 10/2016revision 0: initial version
data sheet ADUCM362/aducm363 rev. 0 | page 3 of 24 general description the ADUCM362 / aducm363 are fully integrated, 3.9 ksps, 24-bit data acquisition systems that incorporate dual, high performance, multichannel sigma-delta (-) analog-to-digital converters (adcs), a 32-bit arm cortex?-m3 processor, and flash/ee memory on a single chip. the ADUCM362 / aducm363 are designed for direct interfacing to external precision sensors in both wired and battery-powered applications. the aducm363 contains all the features of the ADUCM362, except that only one 24-bit - adc (adc1) is available. the ADUCM362 / aducm363 contain an on-chip 32 khz oscillator and an internal 16 mhz high frequency oscillator. the high frequency oscillator is routed through a programmable clock divider from which the operating frequency of the processor core clock is generated. the maximum core clock speed is 16 mhz; this speed is not limited by operating voltage or temperature. the microcontroller core is a low power arm cortex-m3 processor, a 32-bit risc machine that offers up to 20 mips peak performance. the cortex-m3 processor incorporates a flexible, 11-channel dma controller that supports all wired communica- tion peripherals (both spis, both uarts, and i 2 c). also integrated on chip are up to 256 kb of nonvolatile flash/ee memory and 24 kb of sram. the analog subsystem consists of dual adcs, each connected to a flexible input mux. both adcs can operate in fully differential and single-ended modes. other on-chip adc features include dual programmable excitation current sources, diagnostic current sources, and a bias voltage generator of avdd_reg/2 (900 mv) to set the common-mode voltage of an input channel. a low-side internal ground switch is provided to allow power-down of an external circuit (for example, a bridge circuit) between conversions. optional input buffers are provided for the analog inputs and the external reference inputs. these buffers can be enabled for all pga gain settings. the adcs contain two parallel filters: a sinc3 or sinc4 filter in parallel with a sinc2 filter. the sinc3 or sinc4 filter is used for precision measurements. the sinc2 filter is used for fast measure- ments and for the detection of step changes in the input signal. the devices contain a low noise, low drift internal band gap reference, but they can be configured to accept one or two external reference sources in ratiometric measurement config- urations. an option to buffer the external reference inputs is provided on chip. a single-channel buffered voltage output dac is also provided on chip. the ADUCM362 / aducm363 integrate a range of on-chip peripherals, which can be configured under microcontroller software control as required in the application. the peripherals include two uarts, i 2 c, and dual spi serial i/o communication controllers; a 19-pin gpio port; two general-purpose timers; a wake-up timer; and a system watchdog timer. a 16-bit pwm controller with six output channels is also provided. the ADUCM362 / aducm363 are specifically designed to operate in battery-powered applications where low power operation is critical. the microcontroller core can be configured in a normal operating mode that consumes 290 a/mhz (including flash/ sram i dd ). an overall system current consumption of 1 ma can be achieved with both adcs on (input buffers off), pga gain of 4, one spi port on, and all timers on. the ADUCM362 / aducm363 can be configured in a number of low power operating modes under direct program control, including a hibernate mode (internal wake-up timer active) that consumes only 4 a. in hibernate mode, peripherals, such as external interrupts or the internal wake-up timer, can wake up the devices. this mode allows the devices to operate with ultralow power while still responding to asynchronous external or periodic events. on-chip factory firmware supports in-circuit serial download via a serial wire interface (2-pin jtag system) and uart; non- intrusive emulation is also supported via the serial wire interface. these features are incorporated into a low cost quickstart? development system that supports this precision analog micro- controller family. the devices operate from an external 1.8 v to 3.6 v voltage supply and are specified over an industrial temperature range of ?40c to +125c.
ADUCM362/aducm363 data sheet rev. 0| page 4 of 24 functional block diagrams 24-bit - ? adc v ref ain0 dac, temp, iovdd/4, avdd/4 sinc3/ sinc4 filter 12-bit dac sinc2 filter on-chip 1.8v analog ldo on-chip 1.8v digital ldo power-on reset on-chip oscillator (1% typ) 16mhz gpio ports uart ports 2spiports i 2 cports 19 general- purpose i/o ports memory 256kb flash 24kb sram dma and interrupt controller timer0 timer1 watchdog wake-up timer pwm serial wire debug, programming and debug arm cortex-m3 processor 16mhz v bias generator precision reference ADUCM362 buffer buffer buffer selectable v ref sources current sources ain1 ain2 dac reset xtalo xtali swdio swclk dvdd_reg avdd_reg avdd agnd ain3 ain4/iexc ain5/iexc ain6/iexc a in7/vbias0/iexc/ extref2in+ ain8/extref2in? ain9/dacbuff+ ain10 ain11/vbias1 iref gnd_sw vref? int_ref iovdd iovdd vref+ amp mod2 gain 24-bit - ? adc v ref amp mod2 gain buf buf mux sinc3/ sinc4 filter - ? modulator - ? modulator 14919-001 figure 1. ADUCM362 functional block diagram
data sheet ADUCM362/aducm363 rev. 0 | page 5 of 24 ain0 dac, temp, iovdd/4, avdd/4 12-bit dac sinc2 filter on-chip 1.8v analog ldo on-chip 1.8v digital ldo power-on reset on-chip oscillator (1% typ) 16mhz gpio ports uart ports 2 spi ports i 2 c ports 19 general- purpose i/o ports memory 256kb flash 24kb sram dma and interrupt controller timer0 timer1 watchdog wake-up timer pwm serial wire debug, programming and debug arm cortex-m3 processor 16mhz v bias generator precision reference aducm363 buffer buffer buffer selectable v ref sources current sources ain1 ain2 dac reset xtalo xtali swdio swclk dvdd_reg avdd_reg avdd agnd ain3 ain4/iexc ain5/iexc ain6/iexc ain7/vbias0/iexc/ extref2in+ ain8/extref2in? ain9/dacbuff+ ain10 ain11/vbias1 iref gnd_sw vref? int_ref iovdd iovdd vref+ - ? modulator 24-bit - ? adc v ref sinc3/ sinc4 filter amp mod2 gain buf mux 14919-014 figure 2. aducm363 functional block diagram
ADUCM362/aducm363 data sheet rev. 0| page 6 of 24 specifications microcontroller electr ical specifications avdd/iovdd = 1.8 v to 3.6 v, internal 1.2 v reference, f core = 16 mhz, all specifications at t a = ?40c to +125c, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit adc specifications adc0 and adc1 conversion rate 1 chop off 3.5 3906 hz chop on 3.5 1302 hz no missing codes 1 chop off, f adc 500 hz 24 bits chop on, f adc 250 hz 24 bits rms noise and data output rates s ee table 2 through table 9 integral nonlinearity 1 gain = 1, input buffer off 10 ppm of fsr gain = 2, 4, 8, or 16 15 ppm of fsr gain = 32, 64, or 128 20 ppm of fsr offset error 2, 3, 4, 6, 7 chop off; offset error is in the order of the noise for the programmed gain and update rate following calibration 230/gain v chop on 1 1.0 v offset error drift vs. temperature 1, 4, 6 chop off, gain 4 1/gain v/c chop off, gain 8 230 nv/c chop on 10 nv/c offset error lifetime stability 5 gain = 128 1 v/1000 hr full-scale error 1, 4, 6, 7, 8 0.5/gain mv full-scale error lifetime stability 5 gain = 128 70 v/1000 hr gain error drift vs. temperature 1, 4, 6 external reference gain = 1, 2, 4, 8, or 16 3 ppm/c gain = 32, 64, or 128 6 ppm/c pga gain mismatch error 0.15 % power supply rejection 1 external reference chop on, adc input = 0.25 v, gain = 4 95 db chop off, adc input = 7.8 mv, gain = 128 80 db chop off, adc input = 1 v, gain = 1 90 db absolute input voltage range unbuffered mode agnd avdd v buffered mode available for all gain settings g = 1 to 128 agnd + 0.1 avdd ? 0.1 v differential input voltage ranges 1 for gain = 32, 64, and 128, see table 3 and table 7 for allowable input ranges and noise values gain = 1 v ref v gain = 2 500 mv gain = 4 250 mv gain = 8 125 mv gain = 16 62.5 mv common-mode voltage, v cm 1 ideally, v cm = ((ain+) + (ain?))/2; gain = 2 to 128; input current varies with v cm (see figure 9 and figure 10) agnd avdd v
data sheet ADUCM362/aducm363 rev. 0 | page 7 of 24 parameter test conditions/comments min typ max unit input current 9 buffered mode gain > 1 (excluding ain4, ain5, ain6, and ain7 pins) 1 na gain > 1 (ain4, ain5, ain6, and ain7 pins) 2 na unbuffered mode input current varies with input voltage 860 na/v average input current drift 1 buffered mode ain1, ain3, ain5, ain7, and ain11 5 pa/c ain0, ain4, ain9, and ain10 9 pa/c ain2, ain6, and ain8 15 pa/c unbuffered mode 250 pa/v/c common-mode rejection, dc 1 on adc input adc gain = 1, avdd < 2 v 65 100 db adc gain = 1, avdd > 2 v 80 100 db adc gain = 2 to 128 80 db common-mode rejection, 50 hz/60 hz 1 50 hz/60 hz 1 hz; f adc = 16.67 hz, chop on; f adc = 50 hz, chop off adc gain = 1 97 db adc gain = 2 to 128 90 db normal mode rejection, 50 hz/60 hz 1 on adc input 50 hz/60 hz 1 hz; f adc = 16.67 hz, chop on; f adc = 50 hz, chop off 60 80 db temperature sensor 1 after user calibration voltage output at 25c processor powered down or in standby mode before measurement 82.1 mv voltage temperature coefficient (tc) 250 v/c accuracy 6 c ground switch on resistance (r on ) 3.7 10 19 allowable current 1 20 k resistor off, direct short to ground 20 ma voltage reference adc internal reference internal v ref 1.2 v initial accuracy measured at t a = 25c ?0.1 +0.1 % reference temperature coefficient (tc) 1, 10 ?15 5 +15 ppm/c power supply rejection 1 82 90 db external reference inputs input range buffered mode agnd + 0.1 avdd ? 0.1 v unbuffered mode minimum differential voltage between vref+ and vref? pins is 400 mv 0 avdd v input current buffered mode ?20 +10 +27 na unbuffered mode 500 na/v normal mode rejection 1 80 db common-mode rejection 1 85 100 db reference detect levels 1 400 mv
ADUCM362/aducm363 data sheet rev. 0| page 8 of 24 parameter test conditions/comments min typ max unit excitation current sources output current available from each current source; value programmable from 10 a to 1 ma 10 1000 a initial tolerance at 25c 1 i out 50 a 5 % drift 1 using internal reference resistor 100 400 ppm/c using external 150 k reference resistor between iref pin and agnd; resistor must have drift specification of 5 ppm/c 75 400 ppm/c initial current matching at 25c 1 matching between both current sources 0.5 % drift matching 1 50 ppm/c load regulation, avdd 1 avdd = 3.3 v 0.2 %/v output compliance 1 i out = 10 a to 210 a agnd ? 0.03 avdd ? 0.85 v i out > 210 a agnd ? 0.03 avdd ? 1.1 v dac channel specifications r l = 5 k, c l = 100 pf voltage range internal reference 0 v ref v external reference 0 1.8 v dc specifications 11 resolution 12 bits relative accuracy 3 lsb differential nonlinearity guaranteed monotonic 0.5 1 lsb offset error 1.2 v internal reference 2 10 mv gain error v ref range (reference = 1.2 v) 0.5 % npn mode 1 resolution 12 bits relative accuracy 3 lsb differential nonlinearity 0.5 lsb offset error 0.35 ma gain error 0.75 ma output current range 0.008 23.6 ma interpolation mode 1, 12 only monotonic to 14 bits resolution 14 bits relative accuracy for 14-bit resolution 6 lsb differential nonlinearity monotonic (14 bits) 0.6 lsb offset error 1.2 v internal reference 2 mv gain error v ref range (reference = 1.2 v) 1 % avdd range 1 % dac ac characteristics 1 voltage output settling time 10 s digital-to-analog glitch energy 1 lsb change at major carry (maximum number of bits changes simultaneously in the dac0dat register) 20 nv-sec power-on reset (por) por trip level voltage at dvdd pin power-on level 1.65 v power-down level 1.65 v timeout from por 1 50 ms watchdog timer ( wdt ) 1 timeout period 0.00003 8192 sec timeout step size t3con[3:2] = 10 7.8125 ms flash/ee memory 1 endurance 13 10,000 cycles data retention 14 t j = 85c 10 years
data sheet ADUCM362/aducm363 rev. 0 | page 9 of 24 parameter test conditions/comments min typ max unit digital inputs all digital inputs input leakage current digital inputs except for the reset , swclk, and swdio pins logic 1 v inh = iovdd or v inh = 1.8 v 140 a internal pull-up disabled 1 na logic 0 v inl = 0 v 160 a internal pull-up disabled 10 na input leakage current reset , swclk, and swdio pins logic 1 140 a logic 0 160 a input capacitance 1 10 pf logic input voltage low, v inl 0.2 iovdd v high, v inh 0.7 iovdd v logic output voltage high, v oh i source = 1 ma iovdd ? 0.4 v low, v ol i sink = 1 ma 0.4 v crystal oscillator 1 32.768 khz crystal inputs logic input voltage, xtali only 15 low, v inl 0.8 v high, v inh 1.7 v xtali capacitance 6 pf xtalo capacitance 6 pf on-chip low power oscillator oscillator frequency 32.768 khz accuracy ?30 10 +30 % on-chip high frequency oscillator oscillator frequency 16 mhz accuracy ?40c to +125c ?1.8 +1.4 % long term stability 5 0.8 c/1000 hr processor clock rate 1 nine programmable core clock selections within specified range 0.0625 0.5 16 mhz using an external clock 0.032768 16 mhz processor start-up time 1 at power-on includes kernel power-on execution time 41 ms after reset event includes kernel power-on execution time 1.44 ms from processor power-down (mode 1, mode 2, and mode 3) f clk is the cortex-m3 core clock 3 to 5 f clk from total halt or hibernate mode (mode 4 or mode 5) 30.8 s
ADUCM362/aducm363 data sheet rev. 0| page 10 of 24 parameter test conditions/comments min typ max unit power requirements power supply voltages, v dd avdd, iovdd 1.8 3.6 v power consumption i dd (mcu active mode) 16, 17 processor clock rate = 16 mhz; all peripherals on (clksysdiv = 0) 5.5 ma processor clock rate = 8 mhz; all peripherals on (clksysdiv = 1) 3 ma processor clock rate = 500 khz; both adcs on (input buffers off ) with pga gain = 4, 1 spi port on, all timers on 1 ma i dd (mcu powered down) full temperature range, total halt mode (mode 4) 4 a i dd , total (adc0) 17 pga enabled, gain 32 320 a pga gain = 4, 8, or 16, pga only 130 a gain = 32, 64, or 128, pga only 180 a input buffers 2 input buffers = 70 a 70 a digital interface and modulator 70 a i dd (adc1) input buffers off, gain = 4, 8, or 16 only 200 a external reference input buffers 60 a each 120 a 1 these numbers are not production tested, but are guaranteed by design and/or characterization data at production release. 2 tested at gain = 4 after initial offset calibration. 3 measured with an internal short. a system zero-scale calibration removes this error. 4 a recalibration at any temp erature removes these errors. 5 the long term stability specification is noncumulative. the drift in subsequent 1000 hour periods is sign ificantly lower than in the first 1000 hour period. 6 these numbers do not include internal reference temperature drift. 7 factory calibrated at gain = 1. 8 system calibration at a specific g ain removes the error at this gain. 9 input current is measured with one adc measuri ng a channel. if both adcs measure the same input ch annel, the input current inc reases (approximately doubles). 10 measured using the box method. 11 reference dac linearity is calculated usin g a reduced code range of 0x0ab to 0xf30. 12 measured using a low-pass filt er with r = 1 k, c = 100 nf. 13 endurance is qualified to 10,00 0 cycles as per jedec standard 22, method a117, and is measured at ?40c, +25c, and +125c. ty pical endurance at 25c is 170,000 cycles. 14 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec standard 22, method a117. retention lifetime derates with junction temperature. 15 voltage input levels are relevant only if driving xtal input from a voltage source. if a crystal is connected directly, the in ternal crystal interface determines the common-mode voltage. 16 typical additional supply current consumed during flash/ee memory pr ogram and erase cycles is 7 ma. 17 total i dd for adc includes figures for pga 32, input buffers, digital interface, and the - modulator.
data sheet ADUCM362/aducm363 rev. 0 | page 11 of 24 rms noise resolution of adc0 and adc1 internal reference (1.2 v) table 2 through table 5 provide rms noise specifications for adc0 and adc1 using the internal reference (1.2 v). table 2 and ta ble 3 list the rms noise for both adcs with various gain and output update rate values. table 4 and table 5 list the typical output rms no ise effective number of bits (enob) in normal mode for both adcs with various gain and output update rate values. (peak-to-peak enob is shown in parentheses.) table 2. rms noise vs. gain and output update rate, inte rnal reference (1.2 v), gain = 1, 2, 4, 8, and 16 update rate (hz) chop/sinc adcflt register value rms noise (v) gain = 1, v ref , adcxmde = 0x01 gain = 2, 500 mv, adcxmde = 0x11 gain = 4, 250 mv, adcxmde = 0x21 gain = 8, 125 mv, adcxmde = 0x31 gain = 16, 62.5 mv, adcxmde = 0x41 3.53 on/sinc3 0x8e7c 1.05 0.45 0.23 0.135 0.072 30 off/sinc3 0x007e 2.1 1.37 0.63 0.37 0.22 50 off/sinc3 0x007d 3.7 1.6 0.83 0.47 0.29 100 off/sinc3 0x004d 5.45 2.41 1.13 0.63 0.38 488 off/sinc4 0x100f 10 4.7 2.2 1.3 0.79 976 off/sinc4 0x1007 13.5 6.5 3.3 1.7 1.1 1953 off/sinc4 0x1003 19.3 10 4.7 2.6 1.55 3906 off/sinc4 0x1001 67.0 36 16.6 8.8 4.9 table 3. rms noise vs. gain and output update rate, internal reference (1.2 v), gain = 32, 64, and 128 update rate (hz) chop/ sinc adcflt register value rms noise (v) gain = 32, 1 62.5 mv, adcxmde = 0x49 gain = 32, 1, 2 22.18 mv, adcxmde = 0x51 gain = 64, 3 15.625 mv, adcxmde = 0x59 gain = 64, 3, 4 10.3125 mv, adcxmde = 0x61 gain = 128, 5 7.8125 mv, adcxmde = 0x69 gain = 128, 5, 6 3.98 mv, adcxmde = 0x71 3.53 on/sinc3 0x8e7c 0.067 0.064 0.073 0.055 0.058 0.052 30 off/sinc3 0x007e 0.202 0.2 0.196 0.16 0.174 0.155 50 off/sinc3 0x007d 0.24 0.24 0.25 0.21 0.21 0.2 100 off/sinc3 0x004d 0.35 0.32 0.36 0.27 0.31 0.25 488 off/sinc4 0x100f 0.7 0.67 0.71 0.58 0.62 0.57 976 off/sinc4 0x1007 0.99 0.91 1.01 0.74 0.83 0.7 1953 off/sinc4 0x1003 1.78 1.3 1.48 1.15 1.25 1.0 3906 off/sinc4 0x1001 6.44 2.68 3.59 1.4 2.2 1.4 1 adcxmde = 0x49 sets the pga for a gain of 16 with a modulator gain of 2. the modulator gain of 2 is implemented by adjusting t he sampling capacitors into the modulator. adcxmde = 0x51 sets the pga for a gain of 32 with the modulator gain off. adcxmde = 0x49 has slightly higher noise b ut supports a wider input range. 2 if avdd < 2.0 v and adcxmde = 0x51, the input range is 17.5 mv. 3 adcxmde = 0x59 sets the pga for a gain of 32 with a modulator gain of 2. the modulator gain of 2 is implemented by adjusting t he sampling capacitors into the modulator. adcxmde = 0x61 sets the pga for a gain of 64 with the modulator gain off. adcxmde = 0x59 has slightly higher noise b ut supports a wider input range. 4 if avdd < 2.0 v and adcxmde = 0x 61, the input range is 8.715 mv. 5 adcxmde = 0x69 sets the pga for a gain of 64 with a modulator gain of 2. the modulator gain of 2 is implemented by adjusting t he sampling capacitors into the modulator. adcxmde = 0x71 sets the pga for a gain of 128 with the modulator gain off. adcxmde = 0x69 has slightly higher noise but supports a wider input range. 6 if avdd < 2.0 v and adcxmde = 0x 71, the input range is 3.828 mv.
ADUCM362/aducm363 data sheet rev. 0| page 12 of 24 table 4. typical output rms noise enob in normal mode, in ternal reference (1.2 v), gain = 1, 2, 4, 8, and 16 update rate (hz) chop/sinc enob by input voltage range and gain 1 gain = 1, v ref , adcxmde = 0x01 gain = 2, 500 mv, adcxmde = 0x11 gain = 4, 250 mv, adcxmde = 0x21 gain = 8, 125 mv, adcxmde = 0x31 gain = 16, 62.5 mv, adcxmde = 0x41 3.53 on/sinc3 21.1 (18.4 p-p) 21.1 (18.4 p-p) 21.1 (18.3 p-p) 20.8 (18.1 p-p) 20.7 (18.0 p-p) 30 off/sinc3 20.1 (17.4 p-p) 19.5 (16.8 p-p) 19.6 (16.9 p-p) 19.4 (16.6 p-p) 19.1 (16.4 p-p) 50 off/sinc3 19.3 (16.6 p-p) 19.25 (16.5 p-p) 19.2 (16.5 p-p) 19.0 (16.3 p-p) 18.7 (16.0 p-p) 100 off/sinc3 18.7 (16.0 p-p) 18.66 (15.9 p-p) 18.75 (16.0 p-p) 18.6 (15.9 p-p) 18.3 (15.6 p-p) 488 off/sinc4 17.9 (15.2 p-p) 17.7 (15.0 p-p) 17.8 (15.1 p-p) 17.55 (14.8 p-p) 17.3 (14.5 p-p) 976 off/sinc4 17.4 (14.7 p-p) 17.2 (14.5 p-p) 17.2 (14.5 p-p) 17.2 (14.4 p-p) 16.8 (14.1 p-p) 1953 off/sinc4 16.9 (14.2 p-p) 16.6 (13.9 p-p) 16.7 (14.0 p-p) 16.55 (13.8 p-p) 16.3 (13.6 p-p) 3906 off/sinc4 15.1 (12.4 p-p) 14.8 (12.0 p-p) 14.9 (12.2 p-p) 14.8 (12.1 p-p) 14.6 (11.9 p-p) 1 rms bits are calculated as follows: log 2 ((2 input range )/ rms noise ); peak-to-peak (p-p) bits are calculated as follows: log 2 ((2 input range )/(6.6 rms noise )). table 5. typical output rms noise enob in normal mode , internal reference (1.2 v), gain = 32, 64, and 128 enob by input voltage range and gain 1 update rate (hz) chop/sinc gain = 32, 62.5 mv, adcxmde = 0x49 gain = 32, 22.18 mv, adcxmde = 0x51 gain = 64, 15.625 mv, adcxmde = 0x59 gain = 64, 10.3125 mv, adcxmde = 0x61 gain = 128, 7.8125 mv, adcxmde = 0x69 gain = 128, 3.98 mv, adcxmde = 0x71 3.53 on/sinc3 19.8 (17.1 p-p) 19.4 (16.7 p-p) 18.7 (16.0 p-p) 18.5 (15.8 p-p) 18.0 (15.3 p-p) 17.2 (14.5 p-p) 30 off/sinc3 18.2 (15.5 p-p) 17.75 (15.0 p-p) 17.3 (14.6 p-p) 17.0 (14.25 p-p) 16.45 (13.7 p-p) 15.6 (12.9 p-p) 50 off/sinc3 18.0 (15.2 p-p) 17.5 (14.8 p-p) 16.93 (14.2 p-p) 16.6 (13.86 p-p) 16.2 (13.5 p-p) 15.3 (12.55 p-p) 100 off/sinc3 17.4 (14.7 p-p) 17.1 (14.35 p-p) 16.4 (13.7 p-p) 16.2 (13.5 p-p) 15.6 (12.9 p-p) 15.0 (12.2 p-p) 488 off/sinc4 16.4 (13.7 p-p) 16.0 (13.3 p-p) 15.4 (12.7 p-p) 15.1 (12.4 p-p) 14.6 (11.9 p-p) 13.8 (11.0 p-p) 976 off/sinc4 15.9 (13.2 p-p) 15.6 (12.85 p-p) 14.91 (12.2 p-p) 14.8 (12.0 p-p) 14.2 (11.5 p-p) 13.4 (10.75 p-p) 1953 off/sinc4 15.1 (12.4 p-p) 15.05 (12.3 p-p) 14.4 (11.6 p-p) 14.1 (11.4 p-p) 13.6 (10.9 p-p) 13.0 (10.2 p-p) 3906 off/sinc4 13.2 (10.5 p-p) 14.0 (11.3 p-p) 13.1 (10.4 p-p) 13.8 (11.1 p-p) 12.8 (10.1 p-p) 12.5 (9.75 p-p) 1 rms bits are calculated as follows: log 2 ((2 input range )/ rms noise ); peak-to-peak (p-p) bits are calculated as follows: log 2 ((2 input range )/(6.6 rms noise )).
data sheet ADUCM362/aducm363 rev. 0 | page 13 of 24 external reference (2.5 v) table 6 through table 9 provide rms noise specifications for adc0 and adc1 using the external reference (2.5 v). table 6 and ta ble 7 list the rms noise for both adcs with various gain and output update rate values. table 8 and table 9 list the typical output rms no ise effective enob in normal mode for both adcs with various gain and output update rate values. (peak-to-peak enob is shown in parentheses.) table 6. rms noise vs. gain and output update rate, exte rnal reference (2.5 v), gain = 1, 2, 4, 8, and 16 update rate (hz) chop/sinc dcft register value rms noise (v) gain = 1, v ref , dcxmde = 0x01 gain = 2, 500 mv, dcxmde = 0x11 gain = 4, 250 mv, dcxmde = 0x21 gain = 8, 125 mv, dcxmde = 0x31 gain = 16, 62.5 mv, dcxmde = 0x41 3.53 on/sinc3 0x8e7c 1.1 0.5 0.27 0.17 0.088 30 off/sinc3 0x007e 3 1.4 0.85 0.44 0.27 50 off/sinc3 0x007d 3.9 2.2 0.92 0.46 0.3 100 off/sinc3 0x004d 5.2 2.8 1.25 0.63 0.38 488 off/sinc4 0x100f 9.3 5.0 2.5 1.2 0.75 976 off/sinc4 0x1007 12.5 7 3.5 1.75 1.2 1953 off/sinc4 0x1003 20.0 10 5.7 2.6 1.71 3906 off/sinc4 0x1001 140.0 70.0 35.0 17.2 8.9 table 7. rms noise vs. gain and output update rate, external reference (2.5 v), gain = 32, 64, and 128 update rate (hz) chop/ sinc rms noise (v) dcft register value gain = 32, 1 62.5 mv, dcxmde = 0x49 gain = 32, 1, 2 22.18 mv, dcxmde = 0x51 gain = 64, 3 15.625 mv, dcxmde = 0x59 gain = 64, 3, 4 10.3125 mv, dcxmde = 0x61 gain = 128, 5 7.8125 mv, dcxmde = 0x69 gain = 128, 5, 6 3.98 mv, dcxmde = 0x71 3.53 on/sinc3 0x8e7c 0.076 0.07 0.088 0.06 0.068 0.58 30 off/sinc3 0x007e 0.21 0.22 0.21 0.19 0.175 0.17 50 off/sinc3 0x007d 0.265 0.21 0.27 0.2 0.225 0.19 100 off/sinc3 0x004d 0.37 0.32 0.366 0.28 0.32 0.26 488 off/sinc4 0x100f 0.73 0.7 0.73 0.57 0.64 0.5 976 off/sinc4 0x1007 1.1 0.83 1.01 0.77 0.89 0.75 1953 off/sinc4 0x1003 2.05 1.3 1.6 1.24 1.3 1.1 3906 off/sinc4 0x1001 9.4 4.8 5.1 2.65 3.2 1.88 1 adcxmde = 0x49 sets the pga for a gain of 16 with a modulator gain of 2. the modulator gain of 2 is implemented by adjusting t he sampling capacitors into the modulator. adcxmde = 0x51 sets the pga for a gain of 32 with the modulator gain off. adcxmde = 0x49 has slightly higher noise b ut supports a wider input range. 2 if avdd < 2.0 v and adcxmde = 0x51, the input range is 17.5 mv. 3 adcxmde = 0x59 sets the pga for a gain of 32 with a modulator gain of 2. the modulator gain of 2 is implemented by adjusting t he sampling capacitors into the modulator. adcxmde = 0x61 sets the pga for a gain of 64 with the modulator gain off. adcxmde = 0x59 has slightly higher noise b ut supports a wider input range. 4 if avdd < 2.0 v and adcxmde = 0x 61, the input range is 8.715 mv. 5 adcxmde = 0x69 sets the pga for a gain of 64 with a modulator gain of 2. the modulator gain of 2 is implemented by adjusting t he sampling capacitors into the modulator. adcxmde = 0x71 sets the pga for a gain of 128 with the modulator gain off. adcxmde = 0x69 has slightly higher noise but supports a wider input range. 6 if avdd < 2.0 v and adcxmde = 0x 71, the input range is 3.828 mv.
ADUCM362/aducm363 data sheet rev. 0| page 14 of 24 table 8. typical output rms noise enob in normal mode, ex ternal reference (2.5 v), gain = 1, 2, 4, 8, and 16 update rate (hz) chop/sinc enob by input voltage range and gain 1 gain = 1, v ref , adcxmde = 0x01 gain = 2, 500 mv, adcxmde = 0x11 gain = 4, 250 mv, adcxmde = 0x21 gain = 8, 125 mv, adcxmde = 0x31 gain = 16, 62.5 mv, adcxmde = 0x41 3.53 on/sinc3 22.1 (19.4 p-p) 20.9 (18.2 p-p) 20.8 (18.1 p-p) 20.5 (17.7 p-p) 20.43 (17.7 p-p) 30 off/sinc3 20.7 (18.0 p-p) 19.4 (16.7 p-p) 19.2 (16.4 p-p) 19.1 (16.4 p-p) 18.82 (16.1 p-p) 50 off/sinc3 20.3 (17.6 p-p) 18.8 (16.1 p-p) 19.05 (16.3 p-p) 19.05 (16.3 p-p) 18.66 (15.9 p-p) 100 off/sinc3 19.9 (17.2 p-p) 18.4 (15.7 p-p) 18.6 (15.9 p-p) 18.6 (15.9 p-p) 18.32 (15.6 p-p) 488 off/sinc4 19.0 (16.3 p-p) 17.6 (14.9 p-p) 17.6 (14.9 p-p) 17.7 (14.9 p-p) 17.34 (14.6 p-p) 976 off/sinc4 18.6 (15.9 p-p) 17.1 (14.4 p-p) 17.1 (14.4 p-p) 17.1 (14.4 p-p) 16.66 (13.9 p-p) 1953 off/sinc4 17.9 (15.2 p-p) 16.6 (13.9 p-p) 16.4 (13.7 p-p) 16.55 (13.8 p-p) 16.15 (13.4 p-p) 3906 off/sinc4 15.1 (12.4 p-p) 13.8 (11.1 p-p) 13.8 (11.1 p-p) 13.8 (11.1 p-p) 13.77 (11.05 p-p) 1 rms bits are calculated as follows: log 2 ((2 input range )/ rms noise ); peak-to-peak (p-p) bits are calculated as follows: log 2 ((2 input range )/(6.6 rms noise )). table 9. typical output rms noise enob in normal mode , external reference (2.5 v), gain = 32, 64, and 128 update rate (hz) chop/sinc enob by input voltage range and gain 1 gain = 32, 62.5 mv, adcxmde = 0x49 gain = 32, 22.18 mv, adcxmde = 0x51 gain = 64, 15.625 mv, adcxmde = 0x59 gain = 64, 10.3125 mv, adcxmde = 0x61 gain = 128, 7.8125 mv, adcxmde = 0x69 gain = 128, 3.98 mv, adcxmde = 0x71 3.53 on/sinc3 19.6 (16.9 p-p) 19.3 (16.55 p-p) 18.4 (15.7 p-p) 18.4 (15.7 p-p) 17.8 (15.1 p-p) 17.1 (14.3 p-p) 30 off/sinc3 18.2 (15.5 p-p) 17.6 (14.9 p-p) 17.2 (14.5 p-p) 16.7 (14.0 p-p) 16.4 (13.7 p-p) 15.5 (12.8 p-p) 50 off/sinc3 17.8 (15.1 p-p) 17.7 (15.0 p-p) 16.8 (14.1 p-p) 16.65 (13.9 p-p) 16.1 (13.4 p-p) 15.35 (12.6 p-p) 100 off/sinc3 17.4 (14.6 p-p) 17.1 (14.35 p-p) 16.4 (13.7 p-p) 16.2 (13.4 p-p) 15.6 (12.85 p-p) 14.9 (12.2 p-p) 488 off/sinc4 16.4 (13.7 p-p) 16.0 (13.2 p-p) 15.4 (12.7 p-p) 15.1 (12.4 p-p) 14.6 (11.85 p-p) 14.0 (11.2 p-p) 976 off/sinc4 15.8 (13.1 p-p) 15.7 (13.0 p-p) 14.9 (12.2 p-p) 14.7 (12.0 p-p) 14.1 (11.4 p-p) 13.4 (10.6 p-p) 1953 off/sinc4 14.9 (12.1 p-p) 15.1 (12.3 p-p) 14.25 (11.5 p-p) 14.0 (11.3 p-p) 13.55 (10.8 p-p) 12.8 (10.1 p-p) 3906 off/sinc4 12.7 (10.0 p-p) 13.2 (10.4 p-p) 12.6 (9.9 p-p) 12.9 (10.2 p-p) 12.25 (9.5 p-p) 12.0 (9.3 p-p) 1 rms bits are calculated as follows: log 2 ((2 input range )/ rms noise ); peak-to-peak (p-p) bits are calculated as follows: log 2 ((2 input range )/(6.6 rms noise )).
data sheet ADUCM362/aducm363 rev. 0 | page 15 of 24 i 2 c timing specifications the capacitive load for each i 2 c bus line (c b ) is 400 pf maximum as per the i 2 c bus specifications. i 2 c timing is guaranteed by design, but is not production tested. table 10. i 2 c timing in fast mode (400 khz) parameter description min max unit t l serial clock (scl) low pulse width 1300 ns t h scl high pulse width 600 ns t shd start condition hold time 600 ns t dsu data setup time 100 ns t dhd data hold time 0 ns t rsu setup time for repeated start 600 ns t psu stop condition setup time 600 ns t buf bus free time between a stop cond ition and a start condition 1.3 ? s t r rise time for both scl and serial data (sda) 20 + 0.1 c b 300 ns t f fall time for both scl and sda 20 + 0.1 c b 300 ns t sup pulse width of suppressed spike 0 50 ns table 11. i 2 c timing in standard mode (100 khz) parameter description min max unit t l scl low pulse width 4.7 s t h scl high pulse width 4.0 ns t shd start condition hold time 4.7 s t dsu data setup time 250 ns t dhd data hold time 0 s t rsu setup time for repeated start 4.0 s t psu stop condition setup time 4.0 s t buf bus free time between a stop condit ion and a start condition 4.7 s t r rise time for both scl and sda 1 s t f fall time for both scl and sda 300 ns sda (i/o) t buf msb lsb ack msb 1 9 8 1 scl (i) ps stop condition start condition s(r) repeated start t sup t r t f t f t r t h t l t sup t dsu t dhd t rsu t dhd t dsu t shd t psu 14919-002 figure 3. i 2 c-compatible in terface timing
ADUCM362/aducm363 data sheet rev. 0| page 16 of 24 spi timing specifications table 12. spi master mode timing parameter description min typ max unit t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 0 35.5 ns t dosu data output setup time before sclk edge 1 (spidiv + 1) t uclk ns t dsu data input setup time before sclk edge 58.7 ns t dhd data input hold time after sclk edge 16 ns t df data output fall time 12 35.5 ns t dr data output rise time 12 35.5 ns t sr sclk rise time 12 35.5 ns t sf sclk fall time 12 35.5 ns 1 t uclk = 62.5 ns. it corresponds to the internal 16 mhz clock before the clock divider. sclk (polarity = 0) cs 1/2 sclk cycle sclk (polarity = 1) mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t sh t cs t sl 3/4 sclk cycle t sfs t sr t sf t dr t df t dav t dsu t dhd 14919-003 figure 4. spi master mode timing (phase mode = 1) sclk (polarity = 0) sclk (polarity = 1) mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t sh t sr t sf t dr t df t dav t dosu t dsu t dhd cs 1 sclk cycle t cs t sl 1 sclk cycle t sfs 14919-004 figure 5. spi master mode timing (phase mode = 0)
data sheet ADUCM362/aducm363 rev. 0 | page 17 of 24 table 13. spi slave mode timing parameter description min typ max unit t cs cs to sclk edge 62.5 ns t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 62.5 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 49.1 ns t dsu data input setup time before sclk edge 20.2 ns t dhd data input hold time after sclk edge 10.1 ns t df data output fall time 12 35.5 ns t dr data output rise time 12 35.5 ns t sr sclk rise time 12 35.5 ns t sf sclk fall time 12 35.5 ns t sfs cs high after sclk edge 0 ns 1 t uclk = 62.5 ns. it corresponds to the internal 16 mhz clock before the clock divider. sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso msb bit 6 to bit 1 lsb mosi msb in bit 6 to bit 1 lsb in t dhd t dsu t dav t dr t df t cs 14919-005 figure 6. spi slave mode timing (phase mode = 1) sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso msb bit 6 to bit 1 lsb mosi msb in bit 6 to bit 1 lsb in t dhd t dsu t dav t dr t df t docs t cs 14919-006 figure 7. spi slave mode timing (phase mode = 0)
ADUCM362/aducm363 data sheet rev. 0| page 18 of 24 absolute maximum ratings table 14. parameter rating avdd to agnd ?0.3 v to +3.96 v iovdd to dgnd ?0.3 v to +3.96 v digital input voltage to dgnd ?0.3 v to +3.96 v digital output voltage to dgnd ?0.3 v to +3.96 v analog inputs to agnd ?0.3 v to +3.96 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c esd rating, all pins human body model (hbm) 2 kv field-induced charged device model (ficdm) 850 v peak solder reflow temperature snpb assemblies (10 sec to 30 sec) 240c pb-free assemblies (20 sec to 40 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. close attention to pcb thermal design is required. table 15. thermal resistance package type ja unit cp-48-4 27 c/w esd caution
data sheet ADUCM362/aducm363 rev. 0 | page 19 of 24 pin configuration and fu nction descriptions 1 2 3 p0.7/por/txd1 p0.6/irq2/rxd1 p0.5/irq1/cts 4 p0.4/rts/eclko/rts1 5 p0.3/irq0/cs1/rts1/rts 6 p0.2/mosi1/sda/txd 7 p0.1/sclk1/scl/rxd 2 4 a i n 7 / v b i a s 0 / i e x c / e x t r e f 2 i n + 2 3 a i n 6 / i e x c 2 2 a i n 5 / i e x c 2 1 i r e f 2 0 i n t _ r e f 1 9 d a c 1 8 a v d d _ r e g 1 7 a v d d 1 6 a g n d 1 5 v r e f ? 1 4 v r e f + 1 3 g n d _ s w 4 4 p 1 . 6 / i r q 6 / p w m 4 / m o s i 0 4 5 p 1 . 7 / i r q 7 / p w m 5 / c s 0 4 6 p 2 . 0 / s c l / u a r t c l k 4 7 s w c l k 4 8 s w d i o 4 3 p 1 . 5 / i r q 5 / p w m 3 / s c l k 0 4 2 p 1 . 4 / p w m 2 / m i s o 0 / s d a 4 1 p 1 . 3 / p w m 1 / d s r 4 0 p 1 . 2 / p w m 0 / r i 3 9 p 1 . 1 / i r q 4 / p w m t r i p / d t r 3 8 p 1 . 0 / i r q 3 / p w m s y n c / e x t c l k 3 7 i o v d d top view (not to scale) ADUCM362/ aducm363 25 ain4/iexc 26 ain3 27 ain2 28 ain1 29 ain0 30 dvdd_reg 31 iovdd 32 xtali 33 xtalo 34 p2.2/bm 35 p2.1/sda/uart1dcd/uartdcd notes 1. exposed pad. the lfcsp has an exposed pad that must be soldered to a metal plate on the pcb and to dgnd for mechanical reasons. 36 reset 8 p0.0/miso1/uart1dcd/uartdcd 9 ain11/vbias1 10 ain10 11 ain9/dacbuff+ 12 ain8/extref2in? 14919-007 figure 8. pin configuration table 16. pin function descriptions pin no. mnemonic description 1 reset reset pin, active low input. an internal pull-up is provided. 2 p2.1/sda/uart1dcd/uartdcd general-purpose input/output p2.1/i 2 c serial data pin/uart1 data carrier detect pin/uart data carrier detect pin. 3 p2.2/bm general-purpose input/output p2.2/boot mode inp ut select pin. when this pin is held low during and for a short time after any reset sequence, the devices enter uart download mode. 4 xtalo external crystal oscillator output pin. optional 32.768 khz source for real-time clock. 5 xtali external crystal oscillator input pin. optional 32.768 khz source for real-time clock. 6 iovdd digital system supply pin. this pin must be connected to dgnd via a 0.1 f capacitor. 7 dvdd_reg digital regulator supply. this pin must be co nnected to dgnd via a 470 nf capacitor and to pin 18, avdd_reg. 8 ain0 adc analog input 0. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode. 9 ain1 adc analog input 1. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode. 10 ain2 adc analog input 2. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode. 11 ain3 adc analog input 3. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode. 12 ain4/iexc adc analog input 4/excitation current source. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode (ain4). this pin can also be configured as the output pin for excitation current source 0 or excitation current source 1 (iexc).
ADUCM362/aducm363 data sheet rev. 0| page 20 of 24 pin no. mnemonic description 13 gnd_sw sensor power switch to analog ground reference. 14 vref+ external reference positive input. an extern al reference can be applied between the vref+ and vref? pins. 15 vref? external reference negative input. an extern al reference can be applied between the vref+ and vref? pins. 16 agnd analog system ground reference pin. 17 avdd analog system supply pin. this pin must be connected to agnd via a 0.1 f capacitor. 18 avdd_reg internal analog regulator supply output. this pin must be connected to agnd via a 470 nf capacitor and to pin 7, dvdd_reg. 19 dac dac voltage output. 20 int_ref internal reference. this pin must be connected to ground via a 470 nf decoupling capacitor. 21 iref optional reference current resistor connection for the excitation current sources. the reference current used for the excitation curr ent sources is set by a low drift (5 ppm/c) external resistor connected to this pin. 22 ain5/iexc adc analog input 5/excitation current source. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode (ain5). this pin can also be configured as the output pin for excitation current source 0 or excitation current source 1 (iexc). 23 ain6/iexc adc analog input 6/excitation current source. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode (ain6). this pin can also be configured as the output pin for excitation current source 0 or excitation current source 1 (iexc). 24 ain7/vbias0/iexc/extref2in+ adc analog input 7/bias voltage output/excitation current source/external reference 2 positive input. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode (ain7). this pin can also be configured as an analog output pin to generate a bias voltage, vbias0 of avdd_r eg/2 (vbias0); as the output pin for excitation current source 0 or excitation current source 1 (iexc); or as the positive input for external reference 2 (extref2in+). 25 ain8/extref2in? adc analog input 8/external reference 2 negati ve input. this pin can be configured as a positive or negative input to either adc in diff erential or single-ended mode (ain8). this pin can also be configured as the negative in put for external reference 2 (extref2in?). 26 ain9/dacbuff+ adc analog input 9/noninverting input to the da c output buffer. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode (ain9). this pin can also be configured as the noninverting input to the dac output buffer when the dac is configured for npn mode (dacbuff+). 27 ain10 adc analog input 10. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode. 28 ain11/vbias1 adc analog input 11/bias voltage output. this pin can be configured as a positive or negative input to either adc in differential or single-ended mode (ain11). this pin can also be configured as an analog output pin to generate a bias voltage, vbias1 of avdd_reg/2 (vbias1). 29 p0.0/miso1/uart1dcd/ uartdcd general-purpose input/output p0.0/spi1 master input, slave output pin/uart1 data carrier detect pin/ uart data carrier detect pin. 30 p0.1/sclk1/scl/rxd general-purpose input/output p0.1/spi1 serial clock pin/i 2 c serial clock pin/uart serial input (data input for the uart downloader). 31 p0.2/mosi1/sda/txd general-purpose input/output p0.2/spi1 master output, slave input pin/i 2 c serial data pin/ uart serial output (data output for the uart downloader). 32 p0.3/irq0/cs1 /rts1/rts general-purpose input/output p0.3/external interrupt request 0/spi1 chip select pin (active low) (when using spi1, configure this pin as cs1 )/uart1 request to send signal/uart request to send signal. 33 p0.4/rts/eclko/rts1 general-purpose input/output p0.4/uart reques t to send signal/external clock output pin for test purposes/uart1 request to send signal. 34 p0.5/irq1/cts general-purpose input/output p0.5/exter nal interrupt request 1/uart clear to send signal. 35 p0.6/irq2/rxd1 general-purpose input/output p0.6/e xternal interrupt request 2/uart1 serial input. 36 p0.7/por/txd1 general-purpose input/output p0.7/pow er-on reset pin (active high)/uart1 serial output. 37 iovdd digital system supply pin. this pin must be connected to dgnd via a 0.1 f capacitor. 38 p1.0/irq3/pwmsync/extclk general-purpose input/output p1.0/exter nal interrupt request 3/pwm external synchronization input/external clock input pin. 39 p1.1/irq4/pwmtrip/dtr general-purpose input/output p1.1/external inte rrupt request 4/pwm ex ternal trip input/ uart data terminal ready pin. 40 p1.2/pwm0/ri general-purpose input/output p1.2/pwm0 output/uart ring indicator pin.
data sheet ADUCM362/aducm363 rev. 0 | page 21 of 24 pin no. mnemonic description 41 p1.3/pwm1/dsr general-purpose input/output p1.3/pwm1 output/uart data set ready pin. 42 p1.4/pwm2/miso0/sda general-purpose input/output p1.4/pwm2 outp ut/spi0 master input, slave output pin/i 2 c serial data pin. 43 p1.5/irq5/pwm3/sclk0 general-purpose input/output p1.5/external in terrupt request 5/pwm3 output/spi0 serial clock pin. 44 p1.6/irq6/pwm4/mosi0 general-purpose input/output p1.6/external in terrupt request 6/pwm4 output/spi0 master output, slave input pin. 45 p1.7/irq7/pwm5/cs0 general-purpose input/output p1.7/external interrupt request 7/pwm5 output/spi0 chip select pin (active low) (when using spi0, configure this pin as cs0 ). 46 p2.0/scl/uartclk general-purpose input/output p2.0/i 2 c serial clock pin/input clock pin for uart block only. 47 swclk serial wire debug clock input pin. 48 swdio serial wire debug data input/output pin. ep exposed pad. the lfcsp has an exposed pad that must be soldered to a metal plate on the pcb and to dgnd for mechanical reasons.
ADUCM362/aducm363 data sheet rev. 0| page 22 of 24 typical performance characteristics 60 50 40 30 20 input current (na) 10 0 ?10 0.5 1.0 1.5 common-mode voltage (v) 2.0 2.5 3.0 3.5 0 ?20 ?30 i p i p ? i n i n 14919-008 figure 9. input current vs. common-mode voltage (v cm ), gain = 4, adc input = 250 mv, avdd = 3.6 v, t a = 25c, v cm = ((ain+) + (ain?))/2 5 4 3 2 1 0 input current (na) ?1 ?2 ?3 0.5 1.0 1.5 common-mode voltage (v) 2.0 2.5 3.0 3.5 0 ?4 ?5 i p i p ? i n i n 14919-009 figure 10. input current vs. common-mode voltage (v cm ), gain = 128, adc input = 7.8125 mv, avdd = 3.6 v, t a = 25c, v cm = ((ain+) + (ain?))/2 ?40 ?20 0 20 14000000 12000000 10000000 8000000 6000000 4000000 2000000 40 temperature (c) adc codes 60 80 100 120 14919-010 figure 11. adc codes (decimal values) vs. die temperature 0 50 100 150 200 250 0 200 400 600 800 1000 1200 settling time (ms) capacitance (nf) boost = 0 boost = 30 14919-011 figure 12. vbiasx output settlin g time vs. load capacitance, t a = 25c, iovdd and avdd = 3.3 v 0 5 10 15 20 25 30 0 0.51.01.52.02.53.03.5 pull-up resi s tance (k ? ) voltage (v) 14919-012 figure 13. digital input pin pull-up re sistance value vs. voltage applied to digital pin, t a = 25c, iovdd = 3.4 v 0 10 20 30 40 50 60 0 0.5 1.0 1.5 2.0 pull-up resi s tance (k ? ) voltage (v) 14919-013 figure 14. digital input pin pull-up re sistance value vs. voltage applied to digital pin, t a = 25c, iovdd = 1.8 v
data sheet ADUCM362/aducm363 rev. 0 | page 23 of 24 typical system configuration figure 15 shows a typical ADUCM362/ aducm363 configuration. this figure illustrates some of the hardware considerations. the bottom of the lfcsp package has an exposed pad that must be soldered to a metal plate on the pcb for mechanical reasons and to dgnd. the metal plate of the pcb can be connected to ground. place the 0.47 f capacitor on the avdd_reg and dvdd_reg pins as close to the pins as possible. in noisy environments, an additional 1 nf capacitor can be added to iovdd and avdd. 1 2 3 p0.7/por/txd1 p0.6/irq2/rxd1 p0.5/cts/irq1 4 p0.4/rts/eclko/rts1 5 p0.3/irq0/cs1/rts1/rts 6 p0.2/mosi1/sda/txd 7 p0.1/sclk1/scl/rxd 2 4 a i n 7 / v b i a s 0 / i e x c / e x t r e f 2 i n + 2 3 a i n 6 / i e x c 2 2 a i n 5 / i e x c 2 1 i r e f 2 0 i n t _ r e f 1 9 d a c 1 8 a v d d _ r e g 1 7 a v d d 1 6 a g n d 1 2 p f 1 2 p f 1 5 v r e f ? 1 4 v r e f + 1 3 g n d _ s w 4 4 p 1 . 6 / i r q 6 / p w m 4 / m o s i 0 4 5 p 1 . 7 / i r q 7 / p w m 5 / c s 0 4 6 p 2 . 0 / s c l / u a r t c l k 4 7 s w c l k 4 8 s w d i o s w c l k s w d i o 4 3 p 1 . 5 / i r q 5 / p w m 3 / s c l k 0 4 2 p 1 . 4 / p w m 2 / m i s o 0 4 1 p 1 . 3 / p w m 1 / d s r 4 0 p 1 . 2 / p w m 0 / r i 3 9 p 1 . 1 / i r q 4 / p w m t r i p / d t r 3 8 p 1 . 0 / i r q 3 / p w m s y n c / e x t c l k 3 7 i o v d d ADUCM362/ aducm363 25 ain4/iexc 26 ain3 27 ain2 28 ain1 29 ain0 30 dvdd_reg dvdd dgnd 31 iovdd 32 xtali 33 xtalo 34 p2.2/bm 35 p2.1/sda/uart1dcd/uartdcd 36 reset reset reset reset 8 p0.0/miso1/uart1dcd/uartdcd 9 ain11/vbias1 10 ain10 11 ain9/dacbuff+ 12 ain8/extref2in? 0 . 4 7 f 0 . 4 7 f 0 . 1 f 1 5 0 k ? g n d d g n d s w i o t x s w c l k r x 5 v u s b s w d i o i n t e r f a c e b o a r d c o n n e c t o r s w c l k dvdd dgnd dgnd 0 . 1 f avdd 0 . 4 7 f 0 . 1 f 0 . 1 f 1 f 0 . 1 f 5 6 0 ? 1 . 6 ? i n o u t e n g n d d g n d d g n d d g n d avdd dvdd agnd agnd agnd 4 . 7 f 4 . 7 f adp1720armz-3.3 dgnd 14919-115 figure 15. typical system configuration
ADUCM362/aducm363 data sheet rev. 0| page 24 of 24 outline dimensions 112408-b for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-wkkd. 1 0.50 bsc bottom view top view pin 1 indi c ator 7.00 bsc sq 48 13 24 25 36 37 12 exposed pad p i n 1 i n d i c a t o r 5.20 5.10 sq 5.00 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.25 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18 figure 16. 48-lead lead frame chip scale package [lfcsp] 7 mm 7 mm body and 0.75 mm package height (cp-48-4) dimensions shown in millimeters ordering guide model 1 adcs flash/sram temperature range package description package option ordering quantity ADUCM362bcpz256 dual 24-bit 256 kb/24 kb ?40c to +125c 48-lead lfcsp cp-48-4 ADUCM362bcpz256rl7 dual 24-bit 256 kb/24 kb ?40c to +125c 48-lead lfcsp cp-48-4 750 ADUCM362bcpz128 dual 24-bit 128 kb/16 kb ?40c to +125c 48-lead lfcsp cp-48-4 ADUCM362bcpz128rl7 dual 24-bit 128 kb/16 kb ?40c to +125c 48-lead lfcsp cp-48-4 750 aducm363bcpz256 single 24-bit 256 kb/24 kb ?40c to +125c 48-lead lfcsp cp-48-4 aducm363bcpz256rl7 single 24-bit 256 kb/24 kb ?40c to +125c 48-lead lfcsp cp-48-4 750 aducm363bcpz128 single 24-bit 128 kb/16 kb ?40c to +125c 48-lead lfcsp cp-48-4 aducm363bcpz128rl7 single 24-bit 128 kb/16 kb ?40c to +125c 48-lead lfcsp cp-48-4 750 eval-ADUCM362qspz ADUCM362 quickstart plus development system eval-aducm363qspz aducm363 quickstart plus development system 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d14919-0-10/16(0)

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